1. Field of the Invention
The present invention relates to semiconductor devices, and particularly relates to a semiconductor device which acquires data signals based on a data-strobe signal.
2. Description of the Related Art
According to some proposed schemes, semiconductor devices such as those functioning as memory devices may acquire address signals in synchronism with a clock signal, and input or output data signals in synchronism with a data-strobe signal different from the clock signal with an aim of achieving a stable data input/output at high speed.
FIG. 1 is a timing chart showing operations of a semiconductor device which acquires data in synchronism with a data-strobe signal. This device operations and timings thereof are conceived by the inventors for the sake of showing an example.
FIG. 1 shows a case in which data acquisition is performed based on a DDR (double data rate) scheme acquiring data in synchronism with both rising edges and falling edges of a data-strobe signal. A clock signal CLK is shown at the top, and a data-strobe signal DS is illustrated in the middle. At the bottom in the figure is demonstrated a data signal DQ which is acquired in synchronism with the data-strobe signal DS. The example of FIG. 1 demonstrates data-acquisition timings of a burst-write operation where the burst length is set to 4 to write 4-bit data D0-D3 consecutively.
At a first rising edge (clk1) of the clock signal CLK, a write command and a write address WA1 indicative of a start address are input. The write command is decoded by a command decoder, and is supplied to the write-command latch of the semiconductor device, which in turn supplies a write-enable signal. The write-enable signal activates buffers to receive the data-strobe signal DS and the data signal DQ, respectively. The data signal DQ received by one of the buffers is acquired (latched) by a latch in synchronism with the data-strobe signal DS received by the other one of the buffers. Since it takes some time to generate the write-enable signal and activate the buffers, a time period tDSS from the input of the write command (clk1) to the timing of a first rising edge of the data-strobe signal DS needs to be at least 3 ns, for example.
Data D0 is latched at the first rising edge of the data-strobe signal DS, and data Dl is latched at an immediately following falling edge. A next write address WA2 is internally generated at the second rising edge (clk2) of the clock signal CLK. Data D2 is then latched at an immediately following rising edge of the data-strobe signal DS, and data D3 is latched at a subsequent falling edge.
In the DDR scheme, the data D0 and D1 are latched by two different latches. Immediately after the data D1 is latched, the data D0 and D1 are simultaneously supplied in parallel to the internal circuit of the semiconductor device. Accordingly, data is input at half the cycles of the strobe signal, while the internal circuit operates at the same cycles as that of the strobe signal. The write address at which the data D0 and D1 are stored is WA1. Further, immediately after the latching of the data D3, the data D2 and D3 are simultaneously supplied in parallel to the internal circuit of the semiconductor device. In this case, the write address is WA2.
In the semiconductor device as described above, the data-strobe signal DS input by the user preferably has a timing thereof permitting a tolerable timing margin.
FIG. 2 is a timing chart of a data-acquisition operation in which the first rising edge of a data-strobe signal is delayed by one clock cycle behind the input of a write command.
At a first rising edge (clk1) of the clock signal CLK, a write command and a write address WA1 are input from an external source. The first rising edge of the data-strobe signal DS is delayed relative to the input of the address WA1 by one clock cycle, appearing at a timing clk2. This rising edge of the data-strobe signal DS is used to latch data D0, and a following falling edge is used to latch data D1. A next write address WA2 is internally generated at the second rising edge (clk2) of the clock signal CLK. Data D2 is then latched at a following rising edge of the data-strobe signal DS appearing at a timing clk3, and data D3 is latched at an immediately following falling edge.
Upon the latching of the data D1, the data D0 and D1 are supplied to the internal circuit of the semiconductor device in parallel. The write address for the data D0 and D1 is WA1. A write address which was internally generated by the semiconductor device at an immediately preceding timing (clk2) is, however, WA2. Because of this, a simplistic structure which stores an incoming write address in a conventional buffer results in the write address WA1 being replaced by the write address WA2 by the time when the data D0 and D1 are supplied to the internal circuit.
In order to avoid this, the write addresses WA1 and WA2 need to be successively stored in a shift register or the like, for example. In such a configuration, the write address WA1 would have to be read at a timing when the data D0 and D1 are supplied to the internal circuit, and the write address WA2 would have to be read at a timing at which the data D2 and D3 are supplied to the internal circuit.
Implementing address buffers via shift registers is effective where a clock signal and a data-strobe signal are input at such timings as shown in FIG. 2, but is not applicable to a case where these signals are input at such timings as shown in FIG. 1. Since shift registers need some time to complete shift operations thereof, the shift registers used as the address buffers may not be able to output proper addresses at a time when a write operation of data D0 and D1 starts in FIG. 1.
When the time period tDSS has such a length as shown in FIG. 1, it is required to use a write address acquired at a timing immediately prior to the supply of data to the internal circuit. That is, when the data D0 and D1 are supplied to the internal circuit, for example, the write address acquired immediately before is WA1, so that the write address WA1 needs to be provided to the internal circuit along with the data D0 and D1. In contrast, when the time period tDSS is such a period as shown in FIG. 2, the write address WA2 acquired at an immediately preceding timing should not be used, but the write address WA1 that is acquired at a timing previous to this preceding timing should be used with respect to the data D0 and D1, as described above.
If the data-strobe signal is to permit a tolerable timing margin, there is a need to attend to control of address-read operations so as to read an appropriate address from an address buffer at an appropriate timing.
Accordingly, there is a need for a semiconductor device which allows a data-strobe signal to be provided within a tolerable timing margin when acquiring data in synchronism with the data-strobe signal.
Further, a semiconductor device employing a data-strobe signal acquires data and addresses in synchronism with respective timing signals. That is, data is acquired in response to a data-strobe signal, and addresses are acquired in response to a clock signal. Because of a timing difference between a data acquisition and an address acquisition, it is difficult for an internal circuit to perform accurate data processing and data transfer at high speed by matching data with correct addresses.
Accordingly, there is a need for a semiconductor device which can process data and addresses at high speed when the data and addresses are acquired at different timings.